1. Field
Example embodiments relate to a method of operating a nonvolatile memory, and more particularly, to a method of operating a nonvolatile memory, which improves the stability of programming and/or erasing states by accelerating charge stabilization and recombination of electrons and holes.
2. Description of the Related Art
Non-volatile memory devices are semiconductor memory devices that can preserve stored data even when the supply of power is cut off.
A structure of a memory cell, that is, a basic element of the non-volatile memory device, varies according to the application fields of the non-volatile memory device.
In the case of NAND flash semiconductor memory devices, that is, high-capacity non-volatile semiconductor memory devices, a gate of a transistor may have a structure in which a floating gate storing charges (e.g., data) and a control gate controlling the floating gate are sequentially stacked.
With regard to flash semiconductor memory devices, in order to satisfy the demands for larger memory capacities, the size of the memory cell has been reduced. In addition, in accordance with the reduction of the cell size, a height of the floating gate may also need to be reduced.
In order to maintain a memory property of the memory cell, for example, a retention property for preserving the stored data for a sufficiently long time, and at the same time, to reduce the vertical height of the memory cell, semiconductor memory devices having a SONOS (Silicon-Oxide-Nitride-Oxide-Semiconductor) memory devices using a silicon nitride layer (Si3N4), and not a floating gate as a unit for storing charges and a MOIOS (Metal-Oxide-Insulator-Oxide-Semiconductor) structure such as MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) memory devices, have been suggested. In the case of a SONOS device, silicon is used for the control gate, and in the case of a MONOS device, a metal is used for the control gate.
SONOS and MONOS memory devices use a charge trap layer such as the silicon nitride layer (Si3N4) as a unit for storing charges, instead of a floating gate. That is, in the SONOS and MONOS memory devices, the stacked structure (the floating gate and insulating layers stacked on/under the floating gate) between a substrate and the control gate is substituted by a stacked structure (ONO) in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked in the memory cell. Thus, the SONOS and the MONOS memory devices may be considered charge trap flash (CTF) memory devices wherein a threshold voltage is shifted when the charges are trapped by the nitride layer.
A basic structure of the SONOS type memory device may be as follows. A first silicon oxide layer (SiO2), that is, a tunnel insulating layer, having ends contacting source and drain regions, may be formed on a semiconductor substrate between the source and the drain regions, that is, on a channel region. The first silicon oxide layer may be a layer for tunneling charges. A silicon nitride layer (Si3N4) may be formed on the first silicon oxide layer as a charge trap layer. The silicon nitride layer may be a material layer substantially storing data, and the charges tunneled through the first silicon oxide layer may be trapped by the silicon nitride layer. A silicon oxide layer may be formed on the silicon nitride layer as a blocking insulating layer for blocking the charges from moving upward after passing through the silicon nitride layer. A gate electrode may be formed on the second silicon oxide layer.
However, in the SONOS memory device having the above structure, the dielectric constants of the silicon nitride layer and the silicon oxide layers are relatively low, and a density of a trap site in the silicon nitride layer may not be sufficient. Therefore, an operating voltage of the memory device is higher, and a speed of recording data (programming rate) may not be fast enough and charge retention times in vertical and horizontal directions may not be long enough.
Recently, it has been reported that the programming rate and the retention characteristic may be improved when an aluminum oxide layer (Al2O3) having a larger dielectric constant than that of the silicon oxide layer is used instead of the silicon oxide layer as the blocking insulating layer.
In a CTF memory device having a charge trap layer instead of the floating gate, electrons are injected into the charge trap layer during programming, and holes are injected into the charge trap layer during erasing to remove the electrons stored in the charge trap layer using a recombination of the holes and electrons.
However, the electrons injected in an initial programming procedure for an unused CTF memory device may be trapped by the charge trap layer and localized, and then, the electrons may be spatially spread while being thermalized into a deep trap in the nitride layer. Thus, a threshold voltage of the device may be changed, and thus, it may take some time until the threshold voltage (Vth) is fixed according to thermalization of the located electrons.
The variation of the time-dependent threshold voltage may Vth make it difficult to control a dispersion of the threshold voltage values when an incremental step pulse programming (ISPP) method is used.
According to an ISPP method, program pulse voltages may be applied while increasing the magnitudes thereof, and verifying voltages may be applied to identify the threshold voltage of the memory cell, and then, the above may be repeated until the threshold voltage of the memory cell reaches a desired value. Because the initial threshold voltages of the plurality of memory cells forming the memory device may be highly dispersed, the ISPP method may be used so that all of the memory cells may have the desired threshold voltages in consideration of the dispersion between the threshold voltages in the plurality of memory cells.
However, if the threshold voltage is changed in time, it may be more difficult to control the dispersion between the threshold voltages using the ISPP method, and it is not easy to program the memory cells to have the threshold voltages within a desired range.
When the programmed information is erased, injected holes and the localized electrons or the non-localized electrons that are de-trapped by a field may be recombined, and the remaining holes and the localized electrons that are not completely removed may be re-distributed.
During the recombination of the electrons-holes and the re-distribution of the charges, the threshold voltage of the memory device may be changed, and thus, an effective erase time may be considered as a sum of the times taken to perform the re-combination and the re-distribution, not the time of injecting the holes.
A distribution of lifetimes of the electrons-holes (recombination time) measured after optical pumping in a silicon nitride layer fabricated using a low-pressure chemical vapor deposition (LPCVD) method is disclosed in K. S. Seol et al., Phys. Rev. B 62, 1532 (2000).
The recombination times of the electrons and holes may be distributed over a wide range, for example, from ns to ms. According to an LESR (Light-induced Electron Spin Resonance) measurement result, the recombination time may be several 103 seconds.
The recombination time (τ) of the localized electrons and holes may be calculated using equation 1.τ=τ0exp(2R/R0) (τ0=10-8 s)  (1)
where, R0 denotes a localization length of the electron or the hole, and satisfies R0(E)=[h2/m(Ec−E)]½ or [h2/m(Ev−E)]½, and R denotes a distance between the localized electron and the localized hole.
As shown in equation 1, R0 may be reduced in a deep trap, and the recombination time may be increased in the deep trap.
In the erase mode, the injected holes may be stabilized to a deep energy level as time passes.
In the programming mode or the erase mode, the variation of the threshold voltage may be large when the charges are spatially spread and the thermalization is generated. When the thermalization advances further, the change in threshold voltage may be reduced, however, the charges may be localized to a deeper energy level and thus may be more difficult to move.
Therefore, if the recombination takes a long time, the electrons or the holes that are thermalized and localized to the deep energy level according to the elapsed time may not be able to move, and thus, it may be more difficult to recombine the electrons and the holes. In addition, when the movement of the electrons or the holes is limited due to thermalization, the thermalization time may increase.
In addition, when the recombination time is long, the charges may be thermalized according to the elapsed time, and thus, a sufficient recombination of holes—electrons may not be performed. Due to the incomplete recombination, when the trapped electrons remain after performing the erase operation, dispersion may be increased in the programming operation.
For example, in a state where the electrons, as well as the holes, remain due to incomplete recombination of the electrons and holes in the erase mode, even if the same number of electrons as holes, that remain in a case of complete recombination, are injected, the electrons and the holes may be incompletely recombined, and thus, electrons and the holes may exist together. Even though a number of electrons are additionally injected, the recombination may be still incomplete and thus the holes may still exist. The remaining holes may be recombined with the electrons and may cause the change in the threshold voltage when performing the programming process by repeating the electron injection and the verifying using the ISPP method, and thus, the dispersion in the threshold voltages may increase when the programming is completed.
As described above, the existence of the opposite charge due to the incomplete recombination may cause dispersion in the programming operation, and the increase of the dispersion may be prevented only by completely removing the electrons in the erase mode.
When the opposite charges exist due to incomplete recombination, the recombination of the electrons and holes may be performed in a high temperature storage (HTS) operation, and thus, the threshold voltage value may be changed.
Therefore, when the incomplete recombination occurs due to the long thermalization time and the long recombination time, the stabilities of the erase state and the program state may be degraded, the dispersion of the threshold voltage values may be degraded in the programming or the erasing operation, and the threshold voltage may be changed in the HTS operation.